R5F523E6ADFL - MCU

Renesas

Datasheet Details

32-bit RXv2 CPU core.
Max. operating frequency: 32 MHz Capable of 64 DMIPS in operation at 32 MHz.
Enhanced DSP: 32-bit multiply-accumulate and 16-bit multiplysubtract instructions supported.
Built-in FPU: 32-bit single-precision floating point (compliant to IEEE754).
Divider (fastest instruction execution takes two CPU clock cycles).
Fast interrupt.
CISC Harvard architecture with 5-stage pipeline.
Variable-length instructions, ultra-compact code.
On.

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Published: Aug 10, 2020 |