R5F562TADDFF Datasheet PDF - Renesas 100-MHz 32-bit RX MCUs Specs

R5F562TADDFF - 100-MHz 32-bit RX MCUs

This page provides the datasheet information for the R5F562TADDFF, a member of the RX62 100-MHz 32-bit RX MCUs family.

Datasheet Summary

Description

Maximum operating frequency: 100MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Nine 32-bit r

Features

32-bit RX CPU core.
Max. operating frequency: 100 MHz Capable of 165 DMIPS in operation at 100 MHz.
Single precision 32-bit IEEE-754 floating point.
Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations.
Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle).
Fast interrupt.
Divider (fastest instruction execution takes two CPU clock cycles).
Fast interrup.

Datasheet Details

Part number	R5F562TADDFF
Manufacturer	Renesas
File Size	875.57 KB
Description	100-MHz 32-bit RX MCUs
Datasheet	R5F562TADDFF Datasheet
Additional preview pages of the R5F562TADDFF datasheet.

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Full PDF Text Transcription

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DATASHEET RX62T Group, RX62G Group Renesas MCUs R01DS0096EJ0200 100-MHz 32-bit RX MCUs, FPU, 165 DMIPS, 12-bit ADC (3 S/H circuits, double data register, amplifier, comparator): two units, 10-bit ADC one unit, the three ADC units are Rev.2.00 Jan 10, 2014 capable of simultaneous 7-ch. sampling, 100-MHz PWM (two three-phase complementary channels and four single-phase complementary channels or three three-phase complementary channels and one single-phase complementary channel) Features ■ 32-bit RX CPU core  Max.

Published: Feb 17, 2015 |