900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




Renesas Electronics Components Datasheet

R5F5630ACDFP Datasheet

MCU

No Preview Available !

Features
DATASHEET
RX630 Group
Renesas MCUs
R01DS0060EJ0160
Rev.1.60
100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS,
May 19, 2014
up to 2-MB flash memory, USB 2.0 full-speed function interface,
CAN, 10- & 12-bit A/D converter, RTC, up to 22 comms interfaces
Features
32-bit RX CPU core
Max. operating frequency: 100 MHz
Capable of 165 DMIPS in operation at 100 MHz
Single precision 32-bit IEEE-754 floating point
Two types of multiply-and-accumulation unit (between memories
and between registers)
32-bit multiplier (fastest instruction execution takes one CPU
clock cycle)
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
Two types of debugging interfaces: JTAG and FINE (two-line)
Low-power design and architecture
Operation from a single 2.7- to 3.6-V supply
Low power consumption: A product that supports all peripheral
functions draws only 500 μA/MHz.
RTC is capable of operation from a dedicated power supply (min.
operating voltage: 2.3 V).
Four low-power modes
On-chip main flash memory, no wait states
100-MHz operation, 10-ns read cycle (no wait states)
384-Kbyte to 2-Mbyte capacities
User code is programmable by on-board or off-board
programming.
On-chip data flash memory
Max. 32 Kbytes, reprogrammable up to 100,000 times
Programming/erasing as background operations (BGOs)
On-chip SRAM, no wait states
32- to 128-Kbyte capacities
For instructions and operands
Can provide backup on deep software standby
DMA
DMAC: Incorporates four channels
DTC
Reset and supply management
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
Clock functions
External crystal oscillator or internal PLL for operation at 4 to 16
MHz
Internal 125-kHz LOCO and 50-MHz HOCO
125-kHz clock for the IWDT
Frequency of the oscillator for sub-clock generation: 32 kHz
Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Time capture function
(for capturing times in response to event-signal input on external
pins)
Independent watchdog timer
125-kHz LOCO clock operation
Useful functions for IEC60730 compliance
Oscillation-stop detection, frequency measurement, CRC, IWDT,
self-diagnostic function for the A/D converter, etc.
PLQP0176KB-A 24 × 24 mm, 0.5-mm pitch
PLQP0144KA-A 20 × 20 mm, 0.5-mm pitch
PLQP0100KB-A 14 × 14 mm, 0.5-mm pitch
PLQP0080KB-A 12 × 12 mm, 0.5-mm pitch
PTLG0177JB-A 8 × 8 mm, 0.5-mm pitch
PTLG0145KA-A 7 × 7 mm, 0.5-mm pitch
PTLG0100KA-A 5.5 × 5.5 mm, 0.5-mm pitch
PLBG0176GA-A 13 × 13 mm, 0.8-mm pitch
Up to 22 communications interfaces
USB 2.0 full-speed function interface (1 channel)
CAN (compliant with ISO11898-1), incorporating 32 mailboxes
(up to 3 channels)
SCI with multiple functionalities (up to 13 channels)
Choose from among asynchronous mode, clock-synchronous
mode, smart-card interface mode, simple SPI, simple I2C, and
extended serial mode.
I2C bus interface for transfer at up to 1 Mbps (up to 4 channels)
RSPI for high-speed transfer (up to 3 channels)
External address space
8 CS areas (8 × 16 Mbytes)
Multiplexed address data or separate address lines are selectable
per area.
8-, 16-, or 32-bit bus space is selectable per area
Up to 20 extended-function timers
16-bit MTU2: input capture, output capture, complementary PWM
output, phase-counting mode (6 channels)
16-bit TPU: input capture, output capture, phase-counting mode
(12 channels)
8-bit TMR (4 channels)
16-bit compare-match timers (4 channels)
A/D converter for 1-MHz operation
Up to 21 12-bit channels, and incorporating 1 sample-and-hold
circuit
Up to 8 10-bit channels, and incorporating 1 sample-and-hold
circuit
Addition of results of A/D conversion (in the 12-bit A/D converter)
self-diagnosis (for the 10-bit A/D converter)
10-bit D/A converter: 2 channels
Temperature sensor for measuring temperature
within the chip
Register write protection function can protect
values in important registers against overwriting.
Up to 148 general I/O port pins for GPIO
5-V tolerance, open drain, input pull-up, switchable driving ability
Unique ID
16-byte ID code is provided for each chip (only for the G version)
Operating temp. range
D version: -40 to +85°C
G version: -40 to +105°C
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 1 of 154


Renesas Electronics Components Datasheet

R5F5630ACDFP Datasheet

MCU

No Preview Available !

RX630 Group
1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 lists the functions of products.
Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs
depending on the pin number on the package and the ROM capacity. For details, see Table 1.2, Comparison of
Functions for Different Packages.
Table 1.1
Outline of Specifications (1/5)
Classification Module/Function
CPU
CPU
Memory
FPU
ROM
Description
Maximum operating frequency: 100 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per state (cycle of the system
clock)
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Nine 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
Floating-point operation instructions: 8
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 × 32 64 bits
On-chip divider: 32 / 32 32 bits
Barrel shifter: 32 bits
Memory protection unit (MPU)
Single precision floating point (32 bits)
Data types and floating-point exceptions in conformance with the IEEE754 standard
Capacity: 384 Kbytes, 512 Kbytes, 768 Kbytes, 1 Mbyte, 1.5 Mbytes, 2 Mbytes
100 MHz, no-wait access
On-board programming: Four types
Off-board programming (parallel programmer mode)
RAM
E2 data flash
Capacity: 64 Kbytes, 96 Kbytes, 128 Kbytes
100 MHz, no-wait access
Capacity: 32 Kbytes
Programming/erasing: 100,000 times
MCU operating modes
Single-chip mode, on-chip ROM enabled extended mode, and on-chip ROM disabled
extended mode (software switching)
Clock
Clock generation circuit
Main clock oscillator, sub-clock oscillator, low-speed/high-speed on-chip oscillator, PLL
frequency synthesizer, and dedicated on-chip oscillator for the IWDT
Main-clock oscillation stop detection
Separate frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clock (PCLK), FlashIF clock (FCLK) and external bus clock (BCLK)
The CPU and other bus masters run in synchronization with the system clock (ICLK):
Up to 100 MHz
Peripheral modules run in synchronization with the peripheral module clock (PCLK):
Up to 50 MHz
Flash IF run in synchronization with the FlashIF clock (FCLK): Up to 50 MHz
Devices connected to the external bus run in synchronization with the external bus
clock (BCLK): Up to 50 MHz
Reset
Voltage detection circuit
RES# pin reset, power-on reset, voltage-monitoring reset, independent watchdog timer
reset, watchdog timer reset, deep software standby reset, and software reset
When the voltage on VCC passes the voltage detection level (Vdet), an internal reset or
internal interrupt is generated.
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 2 of 154



Part Number R5F5630ACDFP
Description MCU
Maker Renesas
Total Page 3 Pages
PDF Download

R5F5630ACDFP Datasheet PDF





Similar Datasheet

1 R5F5630ACDFB MCU
Renesas
2 R5F5630ACDFC MCU
Renesas
3 R5F5630ACDFP MCU
Renesas





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy