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Renesas Electronics Components Datasheet

R5F566TFEDFP Datasheet

MCU

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Features
Datasheet
RX66T Group
R01DS0315EJ0110
Renesas MCUs
160-MHz, 32-bit RX MCU, on-chip FPU, 928 CoreMark, Supportive of 5V power supply,
Rev.1.10
Feb 08, 2019
up to 1-MB flash memory, up to 128-KB SRAM, 32-KB data flash memory, 16-KB SRAM with ECC, Simultaneous sampling with
3 units of 12-bit A/D converter (up to 7 channels), Single-end/pseudo differential input supportive amplifier (6 channels),
Analog comparator (6 channels), 160 MHz PWM (4 channels for 3-phase complementary, 2 channels for 5-phase
complementary, 10 channels for single-phase complementary), 4-channel high-resolution PWM with resolution of 195 ps at the
minimum, Host/function or OTG controller with full-speed USB 2.0 transfer, CAN, Encryption functions (optional)
Features
■ 32-bit RXv3 CPU core
Maximum operating frequency: 160 MHz
Capable of 928 CoreMark in operation at 160 MHz
JTAG and FINE (one-line) debugging interfaces
■ Low-power design and architecture
Operation from a single 2.7- to 5.5-V supply
Four low-power modes
■ On-chip code flash memory
Supports versions with 1 Mbytes/512 Kbytes/256 Kbytes
No wait cycles at up to 120 MHz or when the ROM cache is hit
User code is programmable by on-board or off-board programming.
■ On-chip data flash memory
32 Kbytes, reprogrammable up to 100,000 times
Programming/erasing as background operations (BGOs)
■ On-chip SRAM, no wait states
128K/64 Kbytes of SRAM (no wait states)
16 Kbytes of RAM with ECC (with wait)
■ Data transfer
DMACa: 8 channels
DTCa: 1 channel
■ ELC
Module operation can be initiated by event signals without using
interrupts
Linked operation between modules is possible when the CPU is in
sleep mode
■ Reset and supply management
Power-on reset (POR)
Low voltage detection (LVDA) with voltage settings
■ Clock functions
Frequency of resonator for main clock oscillator: 8 to 24 MHz (this
can be used as the PLL reference clock)
High-speed on-chip oscillator: 16 MHz/18 MHz/20 MHz (this can
be used as the PLL reference clock)
Low-speed on-chip oscillator: 240 kHz
■ Independent watchdog timer
120-kHz IWDT-dedicated on-chip oscillator clock operation
■ Useful functions for IEC60730 compliance
Oscillation-stoppage detection, functions for self-diagnosis and
detection of disconnection for the A/D converter, clock frequency
accuracy measurement circuit, independent watchdog timer, RAM
test-assisting function by DOC, and CRCA, etc.
Register write protection function can protect values in important
registers against overwriting.
■ External bus
Bus clock at 40 MHz (max)
Four CS areas
8- or 16-bit bus space is selectable per area
PLQP0144KA-B 20 × 20 mm, 0.5 mm pitch
PLQP0112JA-B 20 × 20 mm, 0.65 mm pitch
PLQP0100KB-B 14 × 14 mm, 0.5 mm pitch
PLQP0080JA-A 14 × 14 mm, 0.65 mm pitch
PLQP0080KB-B 12 × 12 mm, 0.5 mm pitch
PLQP0064KB-B 10 × 10 mm, 0.5 mm pitch
■ Various communications interfaces
Host/function or OTG controller (1 channel) with full-speed USB
2.0 (USBb) transfer
CAN (compliant with ISO11898-1), incorporating 32 mailboxes
(1 channel)
SCIj and SCIh with multiple functionalities (up to 6 channels)
Choose from among asynchronous mode, clock-synchronous mode,
smart-card interface mode, simplified SPI, simplified I2C, and
extended serial mode.
SCIi with 16-byte transmission and reception FIFOs (1 channel)
I2C bus interface (RIICa) for transfer at up to 400 kbps (fast mode),
capable of SMBus operation (1 channel)
RSPId (1 channel) for transfer at up to 30 Mbps
■ Up to 31 extended-function timers
32-bit GPTW (10 channels): operation at 160 MHz, input capture,
output compare, PWM waveforms: 10 output channels in single-
phase complementary PWM mode/3 output channels in 3-phase
complementary PWM mode/2 output channels in 5-phase
complementary PWM mode, phase-counting mode, linkage with
comparator (counting operation, PWM negate control)
16-bit MTU3d (9 channels): operation at 160 MHz, input capture,
output compare, PWM waveforms: 2 output channels in 3-phase
complementary PWM mode, phase-counting mode
8-bit TMR (8 channels)
16-bit CMT (4 channels)
■ High-resolution PWM waveform generation circuit
(HRPWM): 4 channels
Controlling the timing of rising or falling of the PWM output
waveform for 32-bit GPTW is realized with minimum of 195 ps
resolution (in operation at 160 MHz)
■ 12-bit A/D converter (S12ADH):
total of 30 channels for three units
Up to three 12-bit units of sample-and-hold circuit included
Unit 0 (8 channels for 3 sample-and-hold circuits),
Unit 1 (8 channels for 3 sample-and-hold circuits),
Unit 2 (14 channels)
Programmable gain amplifier with pseudo differential amplification
(3 channels × 2)
■ Analog Comparator (CMPC): 6 channels
■ 12-bit D/A converter: 2 channels
Usable as a reference voltage for the analog comparator
■ Temperature sensor for measuring temperature
within the chip
■ Encryption functions (Trusted Secure IP Lite)
128- or 256-bit key length of AES for ECB, CBC, GCM, others
True random number generator
Unauthorized access to the encryption engine is disabled and
imposture and falsification of information are prevented
Safe management of keys
■ Up to 110 pins for general I/O ports
5-V tolerance, open drain, input pull-up, switchable driving ability
■ Recommended operating temp. range (Topr)
–40C to +85C
–40C to +105C
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 1 of 201


Renesas Electronics Components Datasheet

R5F566TFEDFP Datasheet

MCU

No Preview Available !

RX66T Group
1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different
packages.
Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs
depending on the pin number on the package and the code flash memory capacity. For details, see Table 1.2,
Comparison of Functions for Different Packages.
Table 1.1
Outline of Specifications (1/9)
Classification Module/Function
CPU
CPU
Memory
FPU
Code flash memory
Data flash memory
Unique ID
RAM
RAM with ECC
Description
Maximum operating frequency: 160 MHz
32-bit RX CPU (RXv3)
Minimum instruction execution time: One instruction per state (cycle of the system clock)
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Ten 32-bit registers
Accumulator: Two 72-bit registers
111 instructions
Standard provided instructions: 111
Basic instructions: 77
Single precision floating point instructions: 11
DSP instructions: 23
Addressing modes: 11
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 × 32 → 64 bits
On-chip divider: 32/32 → 32 bits
Barrel shifter: 32 bits
Single-precision (32-bit) floating-point number
Data types and floating-point exceptions in conformance with the IEEE754 standard
Capacity: 1 Mbyte, 512 Kbytes, 256 Kbytes
ROM cache: Operation of an 8-Kbyte instruction fetching cache can be enabled or
disabled (this is disabled by default).
While ROM cache operation is enabled:
- when the cache is hit, one-cycle access up to 160 MHz
- when the cache is missed:
one to two cycles if ICLK ≤ 120 MHz (bus wait: 0 cycles),
two to three cycles if ICLK > 120 MHz (bus wait: 1 cycle).
While ROM cache operation is disabled:
one cycle if ICLK ≤ 120 MHz (bus wait: 0 cycles),
two cycles if ICLK > 120 MHz (bus wait: 1 cycle).
On-board programming: Five types
Off-board programming (parallel programmer mode) (This is not available for 80/64-pin
products)
The trusted memory (TM) function protects against the reading of programs from blocks
8 and 9.
Capacity: 32 Kbytes
Programming/erasing: 100,000 times
12-byte unique ID for the device
Capacity: 128 Kbytes, 64 Kbytes
160 MHz No-wait access
SED (single error detection)
Capacity: 16 Kbytes
00FF C000h to 00FF FFFFh (16 Kbytes)
SEC-DED (single error correction/double error detection)
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 2 of 201



Part Number R5F566TFEDFP
Description MCU
Maker Renesas
Total Page 3 Pages
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