RC32614A Datasheet | Renesas

Features - UPN channel - Generates clocks with 88fs RMS of jitter - Generates 156.25MHz, with other frequencies available - Four differential HCSL outputs - Six DPLL/DCO channels - pliant with ITU-T G.8262.1 and G.8262 - Configurable as digital phase lock loop, digitally controlled oscillator or synthesizer - Generate any frequency from 0.5Hz to 1GHz - Per channel frequency resolution of 1.11 × 10-16 - Channel-to-channel phase skew control with resolution of 1ps - Ten differential / twenty LVCMOS outputs - Time to digital converters measure phase between external clocks with precision of 1ps - 10 × 10 mm (with 0.8mm ball pitch) 144-CABGA package Applications - Reference clock for 112Gbps Ser Des for 100Gbps to 800Gbps transceivers - Wireless infrastructure for 5G network equipment - Open-RAN distribution units (O-DU) - Core and access IP switches/routers - Tele Boundary Clocks (T-BC) and Tele Time Slave Clocks (T-TSC) according to ITU-T G.8273.2 and G.8273.4 - Tele profiles per ITU-T G.8275.1, G.8275.2, or G.8265.1 R31DS0095EU0102 Rev.1.02 Apr 12, 2022 Page 1 © 2021-2022 Renesas Electronics RC32614A Datasheet OSCI OSCO C LK0 C LK1 C LK2 C LK3 System D PLL TOos Fc OD s System APLL C om bo Bus To FODs DPLL / D CO _0 Reference Monitors Reference Switchi ng Sta te Machines PWM Decoders DPLL / D CO...