RC32504A Datasheet | Renesas

Description The RC32504A is a small, low-power timing ponent designed to be placed immediately adjacent to a PHY, switch, ASIC or FPGA that requires several reference clocks with jitter performance less than 100fs. The RC32504A can act as a frequency synthesizer to locally generate the reference clock, a jitter attenuator to perform local clean-up and/or frequency translation of a centrally-supplied reference, a Synchronous Ethernet equipment clock to perform passband filtering and clean-up of network-supplied references or as a DCO for frequency margining or OTN clock applications. The device is a member of the Renesas high-performance Femto Clock2 family. Features - Jitter below 100fs RMS (10k Hz to 20MHz) - pliant with ITU-T G.8262 for synchronous Ethernet/OTN (EEC/OEC) and ITU-T G.8262.1 for enhanced synchronous Ethernet/OTN (e EEC/e OEC) - PLL core consists of fractional-feedback Analog PLL (APLL) which can optionally be steered by a Digital PLL (DPLL) ○ Operates from a 25MHz to 80MHz crystal or XO ○ APLL frequency independent of input/crystal frequency ○ Operates as a frequency synthesizer, jitter attenuator, synchronous equipment slave clock or Digitally Controlled Oscillator (DCO) ○ DPLL loop filter programmable from 0.1Hz to 12k Hz ○ DCO has tuning granularity of < 1ppt - Programmable input buffer supports HCSL, LVDS, or two LVCMOS with no external terminations needed ○ Input frequencies: 1MHz to 800MHz (250MHz for LVCMOS) ○ Reference monitor qualifies/disqualifies input clock - Programmable status output - 4 differential/8 LVCMOS outputs ○ Any frequency from 10MHz to 1GHz (180MHz for LVCMOS) ○ Programmable output buffer supports HCSL (DC-coupled), LVDS/LVPECL/CML (AC-coupled) or two LVCMOS ○ Differential output swing is selectable: 400m V to 800m V ○ Output Enable input with programmable effect - Supports up to 1MHz I2C or up to 20MHz SPI serial processor port - Can configure itself automatically after reset through internal customer-definable One-Time...