RC32504A Description
The RC32504A is a small, low-power timing ponent designed to be placed immediately adjacent to a PHY, switch, ASIC or FPGA that requires several reference clocks with jitter performance less than 100fs. The RC32504A can act as a frequency synthesizer to locally generate the reference clock, a jitter attenuator to perform local clean-up and/or frequency translation of a centrally-supplied reference, a Synchronous...
RC32504A Key Features
- Jitter below 100fs RMS (10kHz to 20MHz)
- pliant with ITU-T G.8262 for synchronous Ethernet/OTN (EEC/OEC) and ITU-T G.8262.1 for enhanced synchronous Ethernet/OTN
- PLL core consists of fractional-feedback Analog PLL (APLL) which can optionally be steered by a Digital PLL (DPLL)
- Programmable input buffer supports HCSL, LVDS, or two LVCMOS with no external terminations needed
- Programmable status output
- 4 differential/8 LVCMOS outputs
- Supports up to 1MHz I2C or up to 20MHz SPI serial
- Can configure itself automatically after reset through internal customer-definable One-Time Programmable (OTP) memory wi
- 4 × 4 mm 24-QFN package
RC32504A Applications
- Jitter below 100fs RMS (10kHz to 20MHz)
- pliant with ITU-T G.8262 for synchronous Ethernet/OTN (EEC/OEC) and ITU-T G.8262.1 for enhanced synchronous Ethernet/OTN (eEEC/eOEC)