HD74LV2GT86A Datasheet | Renesas

Description The HD74LV2GT86A performs the Boolean functions Y = A ⊕ B or Y = AB + AB in positive logic. A mon application is as a true / plement element. If one of the inputs is low, the other input will be reproduced in true form at the output. If one of the inputs is high, the signal on the other input will be reproduced inverted form at the output. The input protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used as a logic- level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook puters), and the low power consumption extends the battery life. Features - The basic gate function is lined up as Renesas uni logic series. - Supplied on emboss taping for high-speed automatic mounting. - TTL patible input level. Supply voltage range : 3.0 to 5.5 V Operating temperature range : - 40 to +85°C - Logic-level translate function 3.0 V CMOS logic → 5.0 V CMOS logic (@VCC = 5.0 V) 1.8 V or 2.5 V CMOS logic → 3.3 V CMOS logic (@VCC = 3.3 V) - All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) - Output current ±6 m A (@VCC = 3.0 V to 3.6 V), ±12 m A (@VCC = 4.5 V to 5.5 V) - All the logical input has hysteresis voltage for the slow transition. - Ordering Information Part Name Package Type Package Code TTP-8DBV Package Abbreviation US Taping Abbreviation (Quantity) E (3,000 pcs/reel) HD74LV2GT86AUSE SSOP-8 pin Rev.2.00, Oct.20.2003, page 1 of 7 .. Outline and Article Indication - HD74LV2GT86A Index band Lot No. Y M W T 8 6 SSOP-8 Marking Y : Year code (the last digit of year) M : Month code W : Week code Function Table Inputs A L L H H H: L: High level Low level B L H L H Output Y L H H L Rev.2.00, Oct.20.2003, page 2 of 7 .. Pin...