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RNA52A10MM Datasheet

Dual CMOS system-RESET IC

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RNA52A10MM
Dual CMOS system–RESET IC
REJ03D0858-0400
Rev.4.00
Feb 23, 2007
Description
The RNA52A10MM incorporates two reset circuits, one with and one without a delay function, allowing the generation
of separate reset signals for a microprocessor and associated system circuits. The detection voltage of each reset
circuit is determined by the value of an external resistor, and the internal reference voltage is 1.0 V. The CMOS
process for the RNA52A10MM means that the device draws only 1.1 µA (typ.). The reset cancellation delay time is
set with a high degree of accuracy by the values of a capacitor and resistor connected with the CD pin. The MR
(manual reset) input pin is provided for the reset circuit with the delay function, and the reset signal is output in
response to a high level on the MR input pin. The MR pin is pulled down by a 2-Minternal resistor. Output pins
Vo1 and Vo2 are open drain.
Features
Two CMOS reset circuits, one with and one without the delay function
Reference voltage: 1.0 V
Reference voltage accuracy: ± 50 mV
Reference voltage hysteresis: 6% (typ.)
Low current consumption: 1.1 µA (typ.)
Delay time set by an external CR circuit
Manual reset input
Open-drain output
MMPAK-8 (8-pin) package
Operating temperature range: – 40 to 85°C
Pin Arrangement
MR 1
Vo1 2
Vo2 3
GND 4
8 VDD
7 Vi1
6 Vi2
5 CD
Application
Power-supply monitoring and resetting for microprocessors
Power supply sequence control for microprocessors
Desktop and laptop PCs
PC peripheral devices such as printers
Digital still cameras, digital video cameras, and PDAs
Battery-driven products
Wireless communications systems
Rev.4.00 Feb 23, 2007 page 1 of 10


Renesas Electronics Components Datasheet

RNA52A10MM Datasheet

Dual CMOS system-RESET IC

No Preview Available !

RNA52A10MM pdf
RNA52A10MM
Functional Block Diagram and Typical application Circuit
VDD1
RS1
RS2
VDD2
RS3
RS4
Vi1
7
Vi2
6
VREF
1.0V
Reset circuit 1
Reset circuit 2
2M
Vo1
2
Vo2
3
VDD3
RL1
VDD4
RL2
RESET
Micro-
computer
VDD
8
MR
1
CD
5
GND
4
RD CD
VDD0
C1
Notes: 1. Please refer to the following equations to set up reset-threshold voltages for power supplies VDD1 and VDD2,
and to set up external voltage-dividing resistor pairs RS1 and RS2, and RS3 and RS4.
(1) VDD1 reset-threshold voltage = VREF × (RS1+RS2)/RS2
(2) VDD2 reset-threshold voltage = VREF × (RS3+RS4)/RS4
Note that values must be set up within the following range: RS1, RS2, RS3, RS4 50 k
See the following graph for the relationship between the reference voltage variation and the value selected
for RS1, RS2, RS3 and RS4.
2. For capacitor C1, select a type which has excellent frequency characteristics. For stable operation, place it
between the VDD pin and the GND pin and as close as is possible to the chip.
The value of capacitor C1 must suit the system environment in terms of the quality of the power supply and so
forth.
5
4
3
2
1
0
-1
0.1
Reference Voltage Variation vs. Parallel Resistance
1 10 100
Parallel Resistance (RS1//RS2, RS3//RS4) [k]
1000
Rev.4.00 Feb 23, 2007 page 2 of 10


Part Number RNA52A10MM
Description Dual CMOS system-RESET IC
Maker Renesas Technology
Total Page 11 Pages
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