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SPARC Technology
Business
Preliminary
STP1030
May 1995
DATA SHEET
UltraSPARC-I
High-Performance 64-Bit RISC Processor
INTRODUCTION
The STP1030, UltraSPARC-I, is a high-performance, highly-integrated superscalar processor implementing the SPARC V9 64-bit RISC architecture. The STP1030 is capable of sustaining the execution of up to four instructions per cycle even in the presence of conditional branches and cache misses. This sustained performance is supported by a decoupled Prefetch and Dispatch Unit with Instruction Buffer to feed the Execution Unit. On the output side of the Execution Unit, Load and Store buffers completely decouple pipeline execution from data cache misses.
STP1030 Datasheet
