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74HC76 Datasheet

DUAL J-K FLIP FLOP

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M74HC76
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
s HIGH SPEED :
fMAX = 67MHz (TYP.) at VCC = 6V
s LOW POWER DISSIPATION:
www.DataSheet4U.comICC =2µA(MAX.) at TA=25°C
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28 % VCC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 76
DESCRIPTION
The M74HC76 is an high speed CMOS DUAL J-K
FLIP FLOP WITH CLEAR fabricated with silicon
gate C2MOS technology.
Depending on with the logic level at J and K
inputs, this device changes state on the negative
going transition of clock pulse (CK). CLEAR (CLR)
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
TSSOP
M74HC76B1R
M74HC76M1R
T&R
M74HC76RM13TR
M74HC76TTR
and PRESET (PR) are independent of the clock
and are accomplished by a logic low on the
corresponding input.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
August 2001
1/11


STMicroelectronics Electronic Components Datasheet

74HC76 Datasheet

DUAL J-K FLIP FLOP

No Preview Available !

M74HC76
INPUT AND OUTPUT EQUIVALENT CIRCUIT
www.DataSheet4U.com
PIN DESCRIPTION
PIN No
1, 6
2, 7
3, 8
4, 9
10, 14
11, 15
16, 12
13
5
SYMBOL NAME AND FUNCTION
1CK, 2CK
Clock Input(HIGH to LOW
edge triggered)
1PR, 2PR Set Inputs (Active LOW)
1CLR, 2CLR
Asynchronous Reset
Inputs (Active LOW)
1J, 2J
Data Inputs: Flip-Flop 1
and 2
1Q, 2Q
Complement Flip-Flop
Outputs
1Q, 2Q True Flip-Flop Outputs
1K, 2K
Data Inputs: Flip-Flop 1
and 2
GND Ground (0V)
Vcc Positive Supply Voltage
TRUTH TABLE
CLR
L
H
L
H
H
H
H
H
X : Don’t Care
PR
H
L
L
H
H
H
H
H
LOGIC DIAGRAM
INPUTS
J
X
X
X
L
L
H
H
X
K
X
X
X
L
H
L
H
X
OUTPUTS
CK Q
Q
XLH
XHL
XHH
Qn Qn
LH
HL
Qn Qn
Qn Qn
FUNCTION
CLEAR
PRESET
----
NO CHANGE
----
----
TOGGLE
NO CHANGE
2/11


Part Number 74HC76
Description DUAL J-K FLIP FLOP
Maker STMicroelectronics
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74HC76 Datasheet PDF






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