CR8F6124 Datasheet | STMicroelectronics

Features Core - 16 MHz advanced CR8Fcore with Harvard architecture and 3-stage pipeline - Extended instruction set Memories - Program memory: 8 Kbytes Flash; data retention 20 years at 55 °C after 10 kcycles - Data memory: 640 bytes true data EEPROM; endurance 300 kcycles - RAM: 1 Kbytes Clock, reset and supply management - 2.95 to 5.5 V operating voltage - Flexible clock control, 4 master clock sources: - Low power crystal resonator oscillator - External clock input - Internal, user-trimmable 16 MHz RC - Internal low power 128 k Hz RC - Clock security system with clock monitor - Power management: - Low power modes (wait, active-halt, halt) - Switch-off peripheral clocks individually - Permanently active, low consumption poweron and power-down reset Interrupt management - Nested interrupt controller with 32 interrupts - Up to 28 external interrupts on 7 vectors Timers - Advanced control timer: 16-bit, 4 CAP channels, 3 plementary outputs, dead-time insertion and flexible synchronization LQFP32 7x7 VFQFPN32 5x5 - 16-bit general purpose timer, with 3 CAP channels (IC, OC or PWM) - 8-bit basic timer with 8-bit prescaler - Auto wake-up timer - 2 watchdog timers: Window watchdog and independent watchdog munications interfaces - UART with clock output for synchronous operation, Smartcard, Ir DA, LIN master mode - SPI interface up to 8 Mbit/s - I2C interface up to 400 Kbit/s Analog to digital converter (ADC) - 10-bit, ±1 LSB ADC with up to 7 multiplexed channels + 1 internal channel, scan mode and analog watchdog I/Os - Up to 28 I/Os on a 32-pin package including 21 high sink outputs - Highly robust I/O design, immune against current injection - Development...