STMicroelectronics Electronic Components Datasheet

M24LR64-R Datasheet

64 Kbit EEPROM

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M24LR64-R

64 Kbit EEPROM with password protection & dual interface:

400 kHz I²C serial bus & ISO 15693 RF protocol at 13.56 MHz

Features

I²C interface

■ Two-wire I2C serial interface

supports 400 kHz protocol

■ Single supply voltage:

– 1.8 V to 5.5 V

■ Byte and Page Write (up to 4 bytes)

■ Random and Sequential Read modes

■ Self-timed programming cycle

■ Automatic address incrementing

■ Enhanced ESD/latch-up protection

Contactless interface

■ ISO 15693 and ISO 18000-3 mode 1 compliant

■ 13.56 MHz ±7k Hz carrier frequency

■ To tag: 10% or 100% ASK modulation using

1/4 (26 Kbit/s) or 1/256 (1.6 Kbit/s) pulse

position coding

■ From tag: load modulation using Manchester

coding with 423 kHz and 484 kHz subcarriers

in low (6.6 kbit/s) or high (26 kbit/s) data rate

mode. Supports the 53 kbit/s data rate with

Fast commands

■ Internal tuning capacitance: 27.5 pF

■ 64-bit unique identifier (UID)

■ Read Block & Write (32-bit Blocks)

Memory

■ 64 Kbit EEPROM organized into:

– 8192 bytes in I²C mode

– 2048 blocks of 32 bits in RF mode

■ Write time

– I²C: 5 ms (Max.)

– RF: 5.75 ms including the internal Verify

time

■ More than 1 Million write cycles in I2C mode

SO8 (MN)

150 mils width

UFDFPN8 (MB)

2 × 3 mm

TSSOP8 (DW)

■ More than 100 000 write cycles in RF mode

■ Multiple password protection in RF mode

■ Single password protection in I2C mode

■ More than 40-year data retention

■ Package

– ECOPACK2® (RoHS compliant and

Halogen-free)

April 2010

Doc ID 15170 Rev 9

1/126

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STMicroelectronics Electronic Components Datasheet

M24LR64-R Datasheet

64 Kbit EEPROM

No Preview Available !

Contents

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M24LR64-R

2/126

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3 Chip Enable (E0, E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.4 Antenna coil (AC0, AC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

User memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

System memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1 M24LR64-R RF block security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.2 Example of the M24LR64-R security protection . . . . . . . . . . . . . . . . . . . . 24

4.3 I2C_Write_Lock bit area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.4 System parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.5 M24LR64-R I2C password security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.5.1 I2C Present Password command description . . . . . . . . . . . . . . . . . . . . 26

4.5.2 I2C Write Password command description . . . . . . . . . . . . . . . . . . . . . . 27

I2C device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.4 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.5 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.6 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.7 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Doc ID 15170 Rev 9

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