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M68Z512 - 4 Mbit 512Kb x8 Low Power SRAM with Output Enable

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General Description

The M68Z512 is a 4 Mbit (4,194,304 bit) CMOS SRAM, organized as 524,288 words by 8 bits.

Overview

M68Z512 4 Mbit (512Kb x8) Low Power SRAM with Output Enable s ULTRA LOW DATA RETENTION CURRENT – 100nA (typical) – 10µA (max) s s s s s s s OPERATION VOLTAGE: 5V ±10% 512 Kbit x8 SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 70ns LOW VCC DATA RETENTION: 2V TRI-STATE COMMON I/O CMOS for OPTIMUM SPEED/POWER AUTOMATIC POWER-DOWN WHEN DESELECTED INTENDED FOR USE WITH ST ZEROPOWER® AND TIMEKEEPER ® CONTROLLERS 32 1 TSOP II 32 (NC) 10 x 20mm s Figure 1.

Key Features

  • fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 5V ±10% supply, and all inputs and outputs are TTL compatible. This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68Z512 is available in a 32 lead TSOP II (10 x 20mm) package. Table 1. Signal Names A0-A18 DQ0-DQ7 E G W VCC VSS Address Inputs VCC 19 A0-A18 8 DQ0-DQ7 W E G M68Z512 Data Input/Outpu.

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