M68Z128 Datasheet (ST Microelectronics) - 5V / 1 Mbit 128Kb x8 Low Power SRAM with Output Enable

M68Z128, 5V / 1 Mbit 128Kb x8 Low Power SRAM with Output Enable

M68Z128 5V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable s ULTRA LOW DATA RETENTION CURRENT 10nA (typical) 2.0µA (max) s s OPERATION VOLTAGE: 5V ±10% 128Kb x 8 VERY FAST SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 55ns LOW VCC DATA RETENTION: 2V TRI-STATE COMMON I/O LOW ACTIVE and STANDBY POWER AUTOMATIC POWER-DOWN WHEN DESELECTED INTENDED FOR USE WITH ST ZEROPOWER® AND TIMEKEEPER ® CONTROLLERS Figure 1.

Logic Diagram TSOP32 (N) 8 x 20mm s s s s s s DES

M68Z128 Features

* fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 5V ±10% supply, and all inputs and outputs are TTL compatible. A0-A16 VCC 17 8 DQ0-DQ7 Table 1. Signal Names A0-A16 DQ0-DQ7 E1 E2 G W VCC VSS NC March 2000 Addre