* fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 5V ±10% supply, and all inputs and outputs are TTL compatible. A0-A16 VCC 17 8 DQ0-DQ7 Table 1. Signal Names A0-A16 DQ0-DQ7 E1 E2 G W VCC VSS NC March 2000 Addre
M68Z128
95.42 KB
5v / 1 mbit 128kb x8 low power sram with output enable.
M68Z128
5V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable
s
ULTRA LOW DATA RETENTION CURRENT
* 10nA (typical)
* 2.0µA (max)
s .
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