M68Z512 Datasheet (ST Microelectronics) - 4 Mbit 512Kb x8 Low Power SRAM with Output Enable

M68Z512, 4 Mbit 512Kb x8 Low Power SRAM with Output Enable

M68Z512 4 Mbit (512Kb x8) Low Power SRAM with Output Enable s ULTRA LOW DATA RETENTION CURRENT 100nA (typical) 10µA (max) s s s s s s s OPERATION VOLTAGE: 5V ±10% 512 Kbit x8 SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 70ns LOW VCC DATA RETENTION: 2V TRI-STATE COMMON I/O CMOS for OPTIMUM SPEED/POWER AUTOMATIC POWER-DOWN WHEN DESELECTED INTENDED FOR USE WITH ST ZEROPOWER® AND TIMEKEEPER ® CONTROLLERS 32 1 TSOP II 32 (NC) 10 x 20mm s Figure 1.

Logic Diagram DES

M68Z512 Features

* fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 5V ±10% supply, and all inputs and outputs are TTL compatible. This device has an automatic power-down feature, reducing the power consumption by over 99% when desel