MK50H27 Datasheet - ST Microelectronics

Signalling System 7 Link Controller

MK50H27 Features

* Complete Level 2 Implementation of SS7. Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols. Optional operation to comply with Japanese TTC JT-Q703 specification requirements Pin-for-pin and architecturally compatible with MK50H25 (X.25/LAPD), MK50H29

MK50H27 General Description

LEGEND: I Input only IO Input / Output OD Open Drain (no internal pull-up) Note: O 3S Output only 3-State Pin out for 52 pin PLCC is shown in brackets. PIN(S) 2-9 40-47 [2-10 44-51] 10 [11] TYPE IO/3S DESCRIPTION The time multiplexed Data/Address bus. During the address portion of a memory transf.

MK50H27 Datasheet (417.62 KB)