MK50H25 Datasheet - ST Microelectronics

MK50H25 HIGH SPEED LINK LEVEL CONTROLLER

(Continued) For added flexibility a transparent mode provides an HDLC transport mechanism without link layer support. This flexible transparent mode may be easily entered and exited without affecting the X.25 link status or the link state variables kept by the MK50H25. In this mode no protocol proce.

MK50H25 Features

* System clock rate up to 33 MHz (MK50H25 33), 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16). Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted On chip DMA control with programmable burst length. DMA transfer rate of up to 13.3 Mbytes/sec using optional 5 SYSCLK DMA cycle (1

MK50H25_STMicroelectronics.pdf