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ST33G640A - Secure MCU

Download the ST33G640A datasheet PDF. This datasheet also covers the ST33G1M2A variant, as both devices belong to the same secure mcu family and are provided as variant models within a single manufacturer datasheet.

General Description

The ST33GxxxA (see Table 1) is a serial access microcontroller designed for secure mobile applications that incorporates the most recent generation of ARM® processors for embedded secure systems.

Key Features

  • Hardware features.
  • ARM® SecurCore® SC300™ 32-bit RISC core cadenced at 25 MHz.
  • 30 Kbytes of user RAM.
  • Up to 1280 Kbytes of user Flash memory with OTP area.
  • Asynchronous receiver transmitter supporting ISO/IEC 7816-3 T=0 and T=1 protocols (Slave mode supported).
  • Single wire protocol (SWP) interface for communications with NFC router (ETSI 102-613 compliant).
  • Serial peripheral interface (SPI) master/slave interface.
  • Three 16-bit timers with interrupt capability.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ST33G1M2A-STMicroelectronics.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by STMicroelectronics

Part Number Description
ST33G1M0A Secure MCU
ST33G1M2 Secure MCU
ST33G1M2A Secure MCU
ST33G384A Secure MCU
ST33G512A Secure MCU

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ST33GxxxA Secure MCU with 32-bit ARM® SecurCore® SC300™ CPU, SWP interface and high-density Flash memory, automotive grade Data brief DFN8 6 × 5 mm Features Hardware features  ARM® SecurCore® SC300™ 32-bit RISC core cadenced at 25 MHz  30 Kbytes of user RAM  Up to 1280 Kbytes of user Flash memory with OTP area  Asynchronous receiver transmitter supporting ISO/IEC 7816-3 T=0 and T=1 protocols (Slave mode supported)  Single wire protocol (SWP) interface for communications with NFC router (ETSI 102-613 compliant)  Serial peripheral interface (SPI) master/slave interface  Three 16-bit timers with interrupt capability  Seven general-purpose I/Os enabling proprietary protocol implementation  1.