STM32MP253C Overview
STM32MP251C/F STM32MP253C/F STM32MP255C/F STM32MP257C/F Includes ST state-of-the-art patented technology. • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up to 400 MHz – L1 16-Kbyte I / 16-Kbyte D – Arm® TrustZone® • 32-bit Arm® Cortex®-M0+ in SmartRun domain – Up to 200 MHz (up to 16 MHz in autonomous mode) • 808-Kbyte internal SRAM: 256-Kbyte AXI SYSRAM, 128-Kbyte AXI video RAM or SYSRAM extension, 256-Kbyte AHB SRAM, 128-Kbyte AHB SRAM with ECC in backup domain, 8-Kbyte SRAM with ECC in backup domain, 32 Kbytes in SmartRun domain • Two Octo-SPI memory interfaces • Flexible external memory controller with up to 16-bit data bus: parallel interface
STM32MP253C Key Features
- Up to 64-bit dual-core Arm® Cortex®-A35
- Up to 1.5 GHz
- 32-Kbyte I + 32-Kbyte D level 1 cache for each core
- 512-Kbyte unified level 2 cache
- Arm® NEON™ and Arm® TrustZone®
- 32-bit Arm® Cortex®-M33 with FPU/MPU
- Up to 400 MHz
- L1 16-Kbyte I / 16-Kbyte D
- Arm® TrustZone®
- 32-bit Arm® Cortex®-M0+ in SmartRun domain