900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




STMicroelectronics Electronic Components Datasheet

STPIC6A259 Datasheet

POWER LOGIC 8-BIT ADDRESSABLE LATCH

No Preview Available !

www.DataSheet4U.com
STPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
s LOW RDS(on): 1TYP
s OUTPUT SHORT-CIRCUIT PROTECTION
s 75mJ AVAILANCHE ENERGY
s EIGHT 350mA DMOS OUTPUTS
s 50V SWITCHING CAPABILITY
s FOUR DISTINCT FUNCTION MODES
s LOW POWER CONSUMPTION
PRELIMINARY DATA
DESCRIPTION
This power logic 8-bit addressable latch controls
open-drain DMOS transistor outputs and is
designed for general-purpose storage
applications in digital systems. Specific uses
include working registers, serial-holding registers,
and decoders or demultiplexers. This is a
multifunctional device capable of operating as
eight addressable latches or an 8-line
demultiplexer with active-low DMOS outputs.
Each open-drain DMOS transistor features an
independent chopping current-limiting circuit to
prevent damage in the case of a short circuit.
Four distinct modes of operation are selectable by
controlling the clear (CLR) and enable (G) inputs
and enumerated in the function table. In the
addressable-latch mode, data at the data-in (D)
terminal is written into the addressed latch. The
addressed DMOS-transistor output inverts the
data input with all unadressed DMOS-transistor
output remaining in their previuous state. In the
MOS-transistor outputs remain in their previous
states and are unaffected by the data or address
inputs. To eliminate the possibility of entering
erroneus data in the latch, enable G should be
SOP
held high (inactive) while the address lines are
changing. In the 8-line demoultiplexing mode, the
addressed output is inverted with respectto the D
input and all other output are high. In the clear
mode, all outputs are high and unaffected by the
address and data inputs.
Separate power ground (PGND) and logic ground
(LGND) terminals are providied to facilitate
maximum system flexibility. All PGND terminals
are interally connected, and each pGND terminal
must be externally connected to the power system
ground in order to minimize parasitic impedance.
A single-point connection between LGND and
PGND must be made externally in a manner that
reduces crosstalk between the logi and load
circuits.
The STPIC6A259 is offered in a termally
enhanced SO-24 package. The STPIC6A259 is
characterized for operation over the operating
case temperature range -40°C to 125°C.
ORDERING CODES
Type
STPIC6A259M
STPIC6A259MTR
Package
SO-24 Batwing (Tube)
SO-24 Batwing (Tape & Reel)
Comments
50parts per tube / 20tube per box
2500 parts per reel
March 2001
1/13
This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.


STMicroelectronics Electronic Components Datasheet

STPIC6A259 Datasheet

POWER LOGIC 8-BIT ADDRESSABLE LATCH

No Preview Available !

www.DataSheet4U.com
STPIC6A259
LOGIC SYMBOL AND PIN CONFIGURATION
FUNCTIONAL TABLE
INPUTS OUTPUT OF EACH
ADDRESSED OTHER FUNCTION
CLR G D
DRAIN
DRAIN
H LH
H LL
H HX
L LH
L LL
L HX
L
H
Qio
L
H
H
Qio Addressable
Qio Latch
Qio Memory
H 8-Line
H Demultiplexer
H Clear
INPUT AND OUTPUT EQUIVALENT CIRCUITS
FUNCTIONAL TABLE
SELECT INPUTS
S2 S1 S0
LLL
LLH
LHL
LHH
HL L
HLH
HH L
HHH
DRAIN ADDRESSED
0
1
2
3
4
5
6
7
2/13


Part Number STPIC6A259
Description POWER LOGIC 8-BIT ADDRESSABLE LATCH
Maker STMicroelectronics
PDF Download

STPIC6A259 Datasheet PDF






Similar Datasheet

1 STPIC6A259 POWER LOGIC 8-BIT ADDRESSABLE LATCH
STMicroelectronics





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z



Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy