STPIC6A259
Description
This power logic 8-bit addressable latch controls open-drain DMOS transistor outputs and is designed for general-purpose storage applications in digital systems.
Key Features
- an independent chopping current-limiting circuit to prevent damage in the case of a short circuit
- Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs and enumerated in the function table
- In the addressable-latch mode, data at the data-in (D) terminal is written into the addressed latch
- The addressed DMOS-transistor output inverts the data input with all unadressed DMOS-transistor output remaining in their previuous state
- In the MOS-transistor outputs remain in their previous states and are unaffected by the data or address inputs
- In the 8-line demoultiplexing mode, the addressed output is inverted with respectto the D input and all other output are high
- In the clear mode, all outputs are high and unaffected by the address and data inputs
- Separate power ground (PGND) and logic ground (LGND) terminals are providied to facilitate maximum system flexibility
- The STPIC6A259 is offered in a termally enhanced SO-24 package
- The STPIC6A259 is characterized for operation over the operating case temperature range -40°C to 125°C
