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STMicroelectronics Electronic Components Datasheet

STi5512 Datasheet

SET TOP BOX BACKEND DECODER

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STi5512 pdf
CONFIDENTIAL® STi5512
SET TOP BOX BACKEND DECODER
WITH INTEGRATED HOST PROCESSOR
PRODUCT PREVIEW
s High performance graphics system
High resolution chroma mode (4:4:4) for RGB output
2 to 8 bits per pixel OSD options
Link list control
4-bit mixing factor by region or 6-bit mixing for each
CLUT entry (anti-aliasing)
8-bit Y, U and V resolution palette
Extra YUV plane for background images or graphics
2D, paced BLT engine with “fill” function
Anti-flicker and anti-flutter filters
s Enhanced 32-bit VL-RISC CPU - 60 MHz clock
Fast integer/bit operation and very high code density
s High performance memory/cache subsystem
2 Kbytes instruction cache, 2 Kbytes data cache or
SRAM, 4 Kbytes SRAM
200 Mbytes/s maximum bandwidth
s Combined video and audio decoder core
Video decoder fully supports MPEG-2 MP@ML.
Letter box (16:9 and 14:9), 2:1, 3:1, 4:1 downsizing
Memory reduction - PAL MP@ML in 12 Mbits
Audio decoder supports layers 1 and 2 of MPEG 1,
and an AC-3 interface to an external decoder
Digital YCrCb output in 4:2:2 format
s PAL/NTSC/SECAM encoder
Outputs RGB with 10-bit DACs and CVBS, Y, C and
component output (YUV) with 10-bit DACS
Separate OSD control for RGB and CVBS outputs
Genlock support
s High performance SDRAM memory interface
Supports two 16- or one 64-Mbit 100 MHz SDRAMs
Accessible by MPEG decoder, PTI, DMAs and CPU
High bandwidth access from CPU allows high
performance OSD operations
s Programmable external memory interface (EMI)
Support for SDRAM included
s Programmable transport interface
Parallel or serial input
Supports DVB bit-streams
More than 32 PIDs supported
DVB descrambler
32 SI/PSI filters of 8 bytes
s Vectored interrupts - 8 prioritized levels
s Interfaces and DMA engines
2 SmartCard interfaces, 2 UARTs, 2 I2C / SPI
controllers, 3 PWM outputs, 4 timers, 3 capture
timers
Block move DMA
Teletext interface, input from external source
IEEE 1284 port, or IEEE 1394 A/V link layer
interface
s Low power controller/real time clock/watchdog
s JTAG Test Access Port
s Professional toolset support
ANSI C compiler and libraries
Advanced debugging tools
s Non-intrusive debug controller
Hardware breakpoints
Real time trace
APPLICATIONS
s Set top boxes to DVB standards.
Block move
DMA
ST20
CPU
Programmable
transport
interface
IEEE 1394
link layer
interface
IEEE 1284
interface
Interrupt
controller
1 OS-Link
2 UARTs
2 I2C
3 PWM
Diagnostic
controller
and system
services
2 SmartCard
interfaces
(ASC)
2 Kbytes
instruction
cache
and 2 Kbytes
data cache
4 Kbytes
SSRRAAMM
EMI
MPEG
audio and
external
decoder I/F
MPEG
video
decoder
PAL/NTSC
/SECAM
encoder
Teletext
interface
10 June 1999
7110123 B
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice


STMicroelectronics Electronic Components Datasheet

STi5512 Datasheet

SET TOP BOX BACKEND DECODER

No Preview Available !

STi5512 pdf
STi5512
1 IntroduFctiIoDn ENTIALThe STi5512 is one of the OMEGA family of integrated multimedia decoder engines for DVB set top box systems. It
offers a high level of integration by reducing the complete set-top box decoding chain from transport demultiplexing to
ONPAL/NTSC/SECAM encoder onto one chip. At the same time it dramatically enhances CPU and graphics performance,
Cand cuts down total system memory cost.
The STi5512 integrates the functions of the MPEG decoder and the PAL/NTSC/SECAM encoder. This single device
includes the following subsystems, which are described in more detail below:
A transport demultiplexor,
A system microcontroller,
A MPEG audio decoder,
A MPEG video decoder,
A PAL/NTSC/SECAM encoder.
The STi5512 minimizes system costs. The external memory interface module (EMI) contains a zero glue logic DRAM/
SDRAM controller and a low cost 32/16/8-bit EPROM interface. SDRAM is supported at the CPU clock rate, 60 MHz.
The SDRAM memory interface directly supports two 16-Mbit or one 64-Mbit 100MHz SDRAM providing the very high
bandwidths to support MPEG decoding and display, on-screen display (OSD) drawing and display, and general system
use. Furthermore the ST20 VL-RISC micro-core has the highest code density of any 32-bit CPU, leading to the lowest
cost program ROM.
The STi5512 is supported by a range of software and hardware development tools for PC and UNIX hosts including an
ANSI-C ST20 software toolset and the ST20 window based debugging toolkit.
Display
The STi5512 provides an enhanced range of display functions and features to improve the video display and add
background and foreground graphics and pictures. Features include:
Five display planes - background color, still picture, decompressed video, on-screen display and sub-picture,
Letterbox filtering,
Anti-flutter and anti-flicker filters,
2- to 8-bits per pixel on-screen display with 24-bit color with anti-aliasing,
Hardware cursor option,
Display memory expandable to 64 Mbits of SDRAM,
2D BLT block move engine,
Two additional display modes for full resolution source video using Frame based filtering for Luma and Chroma.
Video decoder
The video decoder fully supports MPEG-2 Main Profile/Main Level (MP@ML), and has the following features:
A memory reduction architecture, allowing sharing of a single 16-Mbit SDRAM between MPEG decoding, micro and
transport functions.
2/23
7110123 B


Part Number STi5512
Description SET TOP BOX BACKEND DECODER
Maker STMicroelectronics
Total Page 23 Pages
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