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Samsung
Samsung

M366S1723DTS Datasheet Preview

M366S1723DTS Datasheet

PC133/PC100 Unbuffered DIMM

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M366S1723DTS pdf
M366S1723DTS
PC133/PC100 Unbuffered DIMM
M366S1723DTS SDRAM DIMM
16Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
The Samsung M366S1723DTS is a 16M bit x 64 Synchronous
Dynamic RAM high density memory module. The Samsung
M366S1723DTS consists of eight CMOS 16M x 8 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and a
2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy
substrate. One 0.1uF and one 0.22 uF decoupling capacitors
are mounted on the printed circuit board in parallel for each
SDRAM.
The M366S1723DTS is a Dual In-line Memory Module and is
intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth,
high performance memory system applications.
FEATURE
• Performance range
Part No.
M366S1723DTS-C/L7C
M366S1723DTS-C/L7A
M366S1723DTS-C/L1H
M366S1723DTS-C/L1L
Max Freq. (Speed)
133MHz (7.5ns @ CL=2)
133MHz (7.5ns @ CL=3)
100MHz (10ns @ CL=2)
100MHz (10ns @ CL=3)
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB : Height (1,375mil), single sided component
PIN CONFIGURATIONS (Front side/back side)
PIN NAMES
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1 VSS 29 DQM1 57 DQ18 85 VSS 113 DQM5 141 DQ50
2 DQ0 30 CS0 58 DQ19 86 DQ32 114 *CS1 142 DQ51
3 DQ1 31 DU 59 VDD 87 DQ33 115 RAS 143 VDD
4 DQ2 32 VSS 60 DQ20 88 DQ34 116 VSS 144 DQ52
5 DQ3 33 A0 61 NC 89 DQ35 117 A1 145 NC
6 VDD 34 A2 62 *VREF 90 VDD 118 A3 146 *VREF
7 DQ4 35 A4 63 *CKE1 91 DQ36 119 A5 147 NC
8 DQ5 36 A6 64 VSS 92 DQ37 120 A7 148 VSS
9 DQ6 37 A8 65 DQ21 93 DQ38 121 A9 149 DQ53
10 DQ7 38 A10/AP 66 DQ22 94 DQ39 122 BA0 150 DQ54
11 DQ8 39 BA1 67 DQ23 95 DQ40 123 A11 151 DQ55
12 VSS 40 VDD 68 VSS 96 VSS 124 VDD 152 VSS
13 DQ9 41 VDD 69 DQ24 97 DQ41 125 *CLK1 153 DQ56
14 DQ10 42 CLK0 70 DQ25 98 DQ42 126 *A12 154 DQ57
15 DQ11 43 VSS 71 DQ26 99 DQ43 127 VSS 155 DQ58
16 DQ12 44 DU 72 DQ27 100 DQ44 128 CKE0 156 DQ59
17 DQ13 45 CS2 73 VDD 101 DQ45 129 *CS3 157 VDD
18 VDD 46 DQM2 74 DQ28 102 VDD 130 DQM6 158 DQ60
19 DQ14 47 DQM3 75 DQ29 103 DQ46 131 DQM7 159 DQ61
20 DQ15 48 DU 76 DQ30 104 DQ47 132 *A13 160 DQ62
21 *CB0 49 VDD 77 DQ31 105 *CB4 133 VDD 161 DQ63
22 *CB1 50 NC 78 VSS 106 *CB5 134 NC 162 VSS
23 VSS 51 NC 79 CLK2 107 VSS 135 NC 163 *CLK3
24 NC 52 *CB2 80 NC 108 NC 136 *CB6 164 NC
25 NC 53 *CB3 81 NC 109 NC 137 *CB7 165 **SA0
26 VDD 54 VSS 82 **SDA 110 VDD 138 VSS 166 **SA1
27 WE 55 DQ16 83 **SCL 111 CAS 139 DQ48 167 **SA2
28 DQM0 56 DQ17 84 VDD 112 DQM4 140 DQ49 168 VDD
Pin Name
A0 ~ A11
BA0 ~ BA1
DQ0 ~ DQ63
CLK0, CLK2
CKE0
CS0, CS2
RAS
CAS
WE
DQM0 ~ 7
VDD
VSS
*VREF
SDA
SCL
SA0 ~ 2
DU
NC
Function
Address input (Multiplexed)
Select bank
Data input/output
Clock input
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
DQM
Power supply (3.3V)
Ground
Power supply for reference
Serial data I/O
Serial clock
Address in EEPROM
Dont use
No connection
* These pins are not used in this module.
** These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 Sept. 2001



Samsung
Samsung

M366S1723DTS Datasheet Preview

M366S1723DTS Datasheet

PC133/PC100 Unbuffered DIMM

No Preview Available !

M366S1723DTS pdf
M366S1723DTS
PC133/PC100 Unbuffered DIMM
PIN CONFIGURATION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
A0 ~ A11
Address
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA9
BA0 ~ BA1 Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7 Data input/output mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQ0 ~ 63
VDD/VSS
Data input/output
Power supply/ground
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Rev. 0.1 Sept. 2001


Part Number M366S1723DTS
Description PC133/PC100 Unbuffered DIMM
Maker Samsung
Total Page 11 Pages
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