Datasheet Summary
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- M(E)E/N/S/C/L/R
2M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA Features
- 2.5V power supply.
- LVCMOS patible with multiplexed address.
- Four banks operation.
- MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave).
- EMRS cycle with address key programs.
- All inputs are sampled at the positive going edge of the system clock.
- Burst read single-bit write operation.
- Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature pensated Self Refresh)
- DQM for masking.
- Auto refresh.
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- - 64ms refresh period (4K cycle)....
