K4M563233D Datasheet | Samsung Semiconductor

FEATURES - 3.0V & 3.3V power supply - LVCMOS patible with multiplexed address - Four banks operation - MRS cycle with address key programs -. CAS latency (1, 2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) - All inputs are sampled at the positive going edge of the system clock - Burst read single-bit write operation - DQM for masking - Auto & self refresh - 64ms refresh period (4K cycle). - Extended Temperature Operation (-25 °C ~ 85° C). - Inderstrial Temperature Operation (-40 °C ~ 85 ° C). - 90Balls DDP FBGA(-MXXX -Pb, -EXXX -Pb Free). CMOS SDRAM GENERAL DESCRIPTION The K4M283233D is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications. ORDERING INFORMATION Part No. Max Freq. Interface Package 90 FBGA Pb (Pb Free) 125MHz(CL=3) K4M563233D-M(E)E/N/I/P80 105MHz(CL=2) K4M563233D-M(E)E/N/I/P1H 105MHz(CL=2) LVCMOS K4M563233D-M(E)E/N/I/P1L 105MHz(CL=3)- 1 - M(E)E/N ; Normal/Low Power, Temp : -25°C ~ 85° C. - M(E)I/P ; Noraml/Low Power, Temp : -40°C ~ 85° C. Note : 1. In case of 40MHz Frequency, CL1 can be supported. FUNCTIONAL BLOCK DIAGRAM I/O Control LWE Data Input Register LDQM Bank Select 2M x 32 2M x 32 2M x 32 2M x 32 Refresh Counter Output Buffer Row Decoder Sense AMP Row Buffer DQi Address Register CLK ADD Column Decoder Col. Buffer Latency & Burst Length LRAS LCBR LCKE LRAS LCBR LWE LCAS Programming Register LWCBR LDQM Timing...