K7I321882M sram equivalent, 1mx36 & 2mx18 ddrii cio b2 sram.
and the timing waveforms regarding the burst controllability. - Recommended DC operating conditions for Clock added. - AC test conditions for V DDQ=1.8V and Single ended .
Pin Name K, K SA SA0, SA1 DQ CQ, CQ B1 B2 B3 G LBO Pin Description Differential Clocks Synchronous Address Input Synchronous Burst Address Input (SA 0 = LSB) Synchronous Data I/O Differential Output Echo Clocks Load External Address Burst R/W Enable .
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