K7P403623B - 128Kx36 & 256Kx18 SRAM

Samsung semiconductor

K7P403623B Datasheet Preview — Preview of K7P403623B PDF

Datasheet Details

Part number	K7P403623B
Manufacturer	Samsung semiconductor
File Size	344.45 KB
Description	128Kx36 & 256Kx18 SRAM
Datasheet	K7P403623B_Samsungsemiconductor.pdf

K7P403623B Product details

Description

Pin Name K, K SAn DQn SW SWa SWb SWc SWd ZZ Pin Description Differential Clocks(PECL or LVTTL Level) Synchronous Address Input Bi-directional Data Bus Synchronous Global Write Enable Synchronous Byte a Write Enable Synchronous Byte b Write Enable Synchronous Byte c Write Enable Synchronous Byte d Write Enable Asynchronous Power Down Pin Name VDDQ M1, M2 G SS TCK TMS TDI TDO VSS NC Pin Description Output Power Supply Read Protocol Mode Pins ( M1=VDD, M2=VSS ) Asynchronous Output Enable Synchronou

Features

128Kx36 or 256Kx18 Organizations. 3.3V VDD, 2.5/3.3V VDDQ. LVTTL 2.5/3.3V Input and Output Levels. Differential, PECL clock / Single ended or differential LVTTL clock Inputs Synchronous Read and Write Operation Registered Input and Latched Output Internal Pipeline Latches to Support Late Write. Byte Write Capability(four byte write selects, one for each 9 bits) Synchronous or A.

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Published: Apr 25, 2011 |