including:
* A BootRAM and bootloader
* Two independent bi-directional 2KB DataRAM buffers
* A High-Speed x16 Host Interface
* On-chip Error Correction

where Product failure could result in loss of life or personal or physical harm, or any military or defense application,.

5. Added CE don’t care state for Asynch Write, Load, Program, and Block Erase timing diagram 1. Corrected Errata 2. Added Copy-back Program Operation With Random Data Input 3. Pended Active Erase Current 4. Changed tBA from 11ns to 11.5ns Draft Date.

KFH2G16Q2A-DEBx

KFH2G1612M-DEB5

KFH1G16Q2M

KFH4G16Q2M

KF00

KF0602D

KF0604D

KF10N50F

KF10N50FZ

KF10N50P

KF10N50PZ

KF10N60F

KF10N60P