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KM681002B - 128Kx8 Bit High Speed Static RAM

General Description

The KM681002B is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits.

The KM681002B uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.

Key Features

  • Fast Access Time 8,10,12ns(Max. ).
  • Low Power Dissipation Standby (TTL) : 50 mA(Max. ) (CMOS) : 10 mA(Max. ) Operating KM681002B - 8 : 160 mA(Max. ) KM681002B - 10 : 155 mA(Max. ) KM681002B - 12 : 150 mA(Max. ).
  • Single 5.0V ± 10% Power Supply.
  • TTL Compatible Inputs and Outputs www. DataSheet4U. com.
  • I/O Compatible with 3.3V Device.
  • Fully Static Operation - No Clock or Refresh required.
  • Three State Outputs.
  • Center Power/Ground Pin Co.

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Full PDF Text Transcription for KM681002B (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for KM681002B. For precise diagrams, and layout, please refer to the original PDF.

PRELIMINARY KM681002B, KM681002BI Document Title 128Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out. Operated at Commercial and Industrial Temperature ...

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olutionary Pin out. Operated at Commercial and Industrial Temperature Range. Preliminary PRELIMINARY CMOS SRAM Revision History Rev No. Rev. 0.0 Rev.1.0 www.DataSheet4U.com Rev.2.0 History Initial release with Design Target. Release to Preliminary Data Sheet. 1. Replace Design Target to Preliminary. Release to Final Data Sheet. 2.1. Delete Preliminary 2.2. Delete 32-SOJ-300 package 2.3. Delete L-version. 2.4. Delete Data Retention Characteristics and Waveform. 2.5. Add Capacitive load of the test environment in A.C test load 2.6. Change D.C characteristics Previous spec. Changed spec. Items (8/10/12ns part) (8/10/12ns part