during tck(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). 2. The specified values are valid when data inputs (DQ’ s) are.

1 bank 2M x 64, 2M x 72 organisation Optimized for byte-write non-parity or ECC applications Fully PC66 layout compatibl.

PC66 2M x 64 SDRAM module PC66 2M x 72 SDRAM module PC66 2M x 64 SDRAM COB module PC66 2M x 72 SDRAM COB module Pin Names A0-A10 A11 (BS) DQ0 - DQ63 CB0-CB7 RAS CAS WE CKE0 Address Inputs( RA0 ~ RA10 / CA0 ~ CA8) Bank Select Data Input/Output Check.

HYS64V2100GCU-10

HYS64V2100GU-10

HYS64V2200GU-10

HYS64V2200GU-8

HYS64V2200GU-8-3

HYS64V1000GS-10

HYS64V1000GU-50

HYS64V1000GU-60

HYS64V1000GU-70

HYS64V16200GDL

HYS64V16200GDL-7

HYS64V16200GDL-75

HYS64V16200GDL-8