st be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have V il = 0.4 V and V ih = 2.4 V with the timin.

1 bank 8M x 64, 8M x 72 organisation Optimized for byte-write non-parity or ECC applications Fully PC66 layout compatibl.

PC66 8M x 64 SDRAM module PC66 8M x 72 SDRAM module Pin Names A0-A11 BA0,BA1 DQ0 - DQ63 CB0-CB7 RAS CAS WE CKE0 CLK0, CLK1 DQMB0 - DQMB7 CS0 - CS3 Vcc Vss SCL SDA N.C. Address Inputs( RA0 ~ RA11 / CA0 ~ CA8) Bank Selects Data Input/Output Check Bit.

HYS72V8200GU-10

HYS72V8200GU-8

HYS72V1000GU-50

HYS72V1000GU-70

HYS72V128300GR-7-A

HYS72V128300GR-75-A

HYS72V1283201GR-7-D

HYS72V1283201GR-75-C2

HYS72V1283201GR-75-D

HYS72V16200GU-8

HYS72V16200GU-8B

HYS72V16220GU-10

HYS72V16220GU-8