SDA3526-5
Key Features
- It consists of a serial data line SDA and a serial clock line SCL
- The data line requires an external pull-up resistor to VCC (open drain output stage)
- The possible operational states of the I2C Bus are shown in figure - In the quiescent state, both lines SDA and SCL are high, i.e
- the output stage of the data line is disabled
- The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1" is a stop condition
- During a data transfer the information on the data bus will only change while the clock line SCL is "0"
- The information on SDA is valid as long as SCL is "1"
- Between a start and stop condition, information is always transmitted in byte-organized form
- During the output of data, the data output of the memory is high in impedance during the ninth clock pulse (acknowledge master)
- In the case of programming, the active programming process is only started by the stop condition after data input (see figure 3)
