SLA24C16 - 8/16 Kbit (1024/2048 x 8 bit) Serial CMOS-EEPROM
Siemens Semiconductor Group (now Infineon)
Download the SLA24C16 datasheet PDF.
This datasheet also covers the SLA24C08 variant, as both devices belong to the same 8/16 kbit (1024/2048 x 8 bit) serial cmos-eeprom family and are provided as variant models within a single manufacturer datasheet.
General Description
Serial Clock (SCL) The SCL input is used to clock data into the device on the rising edge and to clock data out of the device on the falling edge.
Key Features
Data EEPROM internally organized as 1024/2048 bytes and 64/128 pages × 16 bytes.
Low power CMOS.
VCC = 2.7 to 5.5 V operation.
Two wire serial interface bus, I2C-Bus compatible.
Filtered inputs for noise suppression with Schmitt trigger.
Full PDF Text Transcription for SLA24C16 (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
SLA24C16. For precise diagrams, and layout, please refer to the original PDF.
Standard EEPROM ICs SLx 24C08/16 8/16 Kbit (1024/2048 × 8 bit) Serial CMOS-EEPROM with I2C Synchronous 2-Wire Bus Data Sheet 1998-07-27 http://www.Datasheet4U.com/ SLx 24...
View more extracted text
us 2-Wire Bus Data Sheet 1998-07-27 http://www.Datasheet4U.com/ SLx 24C08/16 Revision History: Previous Version: Page Page (in previous (in current Version) Version) 3 5 4, 5 5 11, 12 15 19 20 20 20 I2C Bus Current Version: 1998-07-27 06.97 Subjects (major changes since last revision) 3 5 4, 5 – 11, 12 15 19 20 20 20 Text was changed to “Typical programming time 5 ms for up to 16 bytes”. WP = VCC protects upper half entire memory. CS0, CS1 and CS2 were replaced by n.c. The paragraph “Chip Select (CS0, CS1, CS2)” was removed completely. The erase/write cycle is finished latest after 10 8 ms. Figure 11: second command byte i
More Datasheets from Siemens Semiconductor Group (now Infineon)
SLA24C16 Datasheet
