SI53106 Datasheet SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Manufacturer: Silicon Laboratories

SI53106 six-output pcie gen 3 buffer/zero delay buffer by Silicon Laboratories - Datasheet Preview

Datasheet Details

Part number	SI53106
Manufacturer	Silicon Laboratories
File Size	1.28 MB
Description	SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER
Datasheet	SI53106 Datasheet

General Description

The Si53106 is a low-power, 6-output, differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification.

The device is optimized for distributing reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications.

The VCO of the device is optimized to support 100 MHz and 133 MHz operation.

Overview

Si53106 SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER.

Key Features

Six 0.7 V low-power, push-pull,.
Low phase jitter (Intel QPI, PCIe HCSL-compatible PCIe Gen 3 Gen 1/2/3/4 common clock outputs compliant.
Individual OE HW pins for each.
Gen 3 SRNS Compliant output clock.
PLL or bypass mode.
100 MHz /133 MHz PLL.
Spread spectrum tolerable.
operation, supports PCIe and QPI PLL bandwidth SW SMBUS programming overrides the latch.
value from HW pin 1.05 to 3.3 V I/O supply voltage 50 ps output-t.

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