SI53106 Key Features
- Six 0.7 V low-power, push-pull
- Low phase jitter (Intel QPI, PCIe
- Individual OE HW pins for each
- Gen 3 SRNS pliant
- PLL or bypass mode
- 100 MHz /133 MHz PLL
- Spread spectrum tolerable
- operation, supports PCIe and QPI
- value from HW pin
- SMBus address configurable to allow multiple buffers in a single