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Si53106 - SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

General Description

The Si53106 is a low-power, 6-output, differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification.

Key Features

  • Six 0.7 V low-power, push-pull,.
  • Low phase jitter (Intel QPI, PCIe HCSL-compatible PCIe Gen 3 Gen 1/2/3/4 common clock outputs compliant.
  • Individual OE HW pins for each.
  • Gen 3 SRNS Compliant output clock.
  • PLL or bypass mode.
  • 100 MHz /133 MHz PLL.
  • Spread spectrum tolerable.
  • operation, supports PCIe and QPI PLL bandwidth SW SMBUS programming overrides the latch.
  • value from HW pin 1.05 to 3.3 V I/O supply voltage 50 ps output-.

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📁 Similar Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Si53106 S IX- O UTPUT P C I E G EN 3 B UFFER/ Z ERO D ELAY B UFFER Features  Six 0.7 V low-power, push-pull,  Low phase jitter (Intel QPI, PCIe HCSL-compatible PCIe Gen 3 Gen 1/2/3/4 common clock outputs compliant  Individual OE HW pins for each  Gen 3 SRNS Compliant output clock  PLL or bypass mode  100 MHz /133 MHz PLL  Spread spectrum tolerable  operation, supports PCIe and QPI PLL bandwidth SW SMBUS programming overrides the latch    value from HW pin 1.05 to 3.3 V I/O supply voltage 50 ps output-to-output skew Industrial Temperature: –40 to 85 °C  SMBus address configurable to allow multiple buffers in a single   40-pin QFN For higher output devices or control network 3.