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Sirenza Microdevices

SLD3091FZ Datasheet Preview

SLD3091FZ Datasheet

30 Watt Discrete LDMOS FET

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Product Description
Sirenza Microdevices’ SLD-3091FZ is a robust 30 Watt high performance
LDMOS transistor designed for operation from 10 to 2200MHz. It is an
excellent solution for applications requiring high linearity and efficiency at a
low cost. The SLD-3091FZ is typically used in power amplifiers, repeaters,
and radio amplifier applications. The power transistor is fabricated using
Sirenza’s high performance XeMOS IITM process.
Preliminary
SLD-3091FZ
Pb RoHS Compliant
& Green Package
30 Watt Discrete LDMOS FET in Ceramic
Flanged Package
Functional Schematic Diagram
ESD
Protection
Product Features
30 Watt Output P1dB
Single Polarity Supply Voltage
High Gain: 18 dB at 915 MHz
High Efficiency: 45% at 30W CW
XeMOS II LDMOS
Integrated ESD Protection, 1B
Case Flange = Ground
Applications
Base Station PA driver
Repeaters
Radio Amplifier
Military Communication
GSM, CDMA, RFID, Point-to-Point
Key RF Specifications
Symbol
Parameter
Frequency
Frequency of Operation
Gain
30 Watt CW, 915 MHz
Efficiency
Drain Efficiency at 30 Watt CW, 915 MHz
IRL
Linearity
RTH
Test Conditions
Input Return Loss, 30 Watt Output Power, 915 MHz
3rd Order IMD at 30 Watt PEP (Two Tone), 915 MHz
1dB Compression (P1dB), 915 MHz
Thermal Resistance (Junction-to-Case)
VDS = 28.0V, IDQ = 300mA, TFlange = 25ºC
T
Units
MHz
dB
%
dB
dBc
Watt
ºC/W
Min.
10
Typ.
-
19
45
-15
-28
35
2.4
Max.
2200
Key DC Parameters
Symbol
Parameter
gm
VGSThreshold
VDS Breakdown
Ciss
Crss
Coss
RDSon
Forward Transconductance @ 425mA IDS
IDS=3mA
1mA IDS current
Input Capacitance (Gate to Source) VGS=0V, VDS=28V
Reverse Capacitance (Gate to Drain) VGS=0V, VDS=28V
Output Capacitance (Drain to Source) VGS=0V, VDS=28V
Drain to Source Resistance, VGS=10V, VDS=250mV
Unit Min Typ. Max
mA / V
1650
Volt 3.3
Volt 65
pF 66
pF 1.4
pF 30
0.2
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such
information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices
does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2005 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 S. Technology Court,
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
1 EDS-104668 Rev C




Sirenza Microdevices

SLD3091FZ Datasheet Preview

SLD3091FZ Datasheet

30 Watt Discrete LDMOS FET

No Preview Available !

Quality Specifications
Parameter
Description
ESD Rating
Human Body Model
Preliminary
SLD-3091FZ 30 Watt LDMOS FET
Rating
1B
Pin Description
Pin #
Function
1 Gate
2
Flange
Drain
Source, Gnd
Description
Transistor RF input and gate bias voltage. The gate bias voltage must be temperature compensated to maintain constant
bias current over the operating temperature range. Care must be taken to protect against video transients that exceed the
recommended maximum input power or voltage.
Transistor RF output and drain bias voltage. Typical voltage is 28V.
Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the board for
optimum thermal and RF performance. See mounting instructions for recommendation.
Pin Diagram
ESD
Protection
Pin 1
Pin 2
Case Flange = Ground
Note 1:
Gate voltage must be applied to the device concurrently or after
application of drain voltage to prevent potentially destructive
oscillations. Bias voltages should never be applied to the tran-
sistor unless it is properly terminated on both input and output.
Note 2:
The required VGS corresponding to a specific IDQ will vary from
device to device due to the normal die-to-die variation in thresh-
old voltage with LDMOS transistors.
Note 3:
The threshold voltage (VGSTH) of LDMOS transistors varies with
device temperature. External temperature compensation may
be required. See Sirenza application notes AN-067 LDMOS
Bias Temperature Compensation.
Absolute Maximum Ratings
Parameters
Value
Unit
Drain Voltage (VDS )
Gate Voltage (VGS)
RF Input Power
35 V
20 V
+36 dBm
Load Impedance for Continuous Operation Without
Damage
10:1
VSWR
Output Device Channel Temperature
+200
ºC
Lead Temperature During Solder Reflow
+270
ºC
Operating Temperature Range
-20 to +90
ºC
Storage Temperature Range
-40 to +100
ºC
Operation of this device beyond any one of these limits may cause perma-
nent damage. For reliable continuous operation see typical setup values
specified in the table on page one.
303 S. Technology Court
Broomfield, CO 80021
Phone: (800) SMI-MMIC
2
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
http://www.sirenza.com
EDS-104668 Rev C


Part Number SLD3091FZ
Description 30 Watt Discrete LDMOS FET
Maker Sirenza Microdevices
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