Description
To be used in conjunction with this data sheet, which contains more detailed explanations about the operation of the device.
Features
- Three independent DSPLLs in a single monolithic IC supporting flexible SyncE/ IEEE 1588 and SETS architectures.
- Ultra-low jitter of 95 fs.
- Enhanced hitless switching minimizes
output phase transients.
- Input frequency range:.
- External crystal: 48 to 54 MHz.
- REF clock: 5 to 250 MHz.
- Diff clock: 8 kHz to 750 MHz.
- LVCMOS clock: 8 kHz to 250 MHz.
- Output frequency range:.
- Differential: 1 PPS to 718.5 MHz.
Si5348 Datasheet
