THC63LVD824A Datasheet | THine Electronics

THC63LVD824A _Rev1.20_E Single(112MHz)/Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA General Description The THC63LVD824A receiver is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA resolutions and Dual Link transmission between Host and Flat Panel Display up to UXGA resolutions. The THC63LVD824A converts the LVDS data streams back into 48bits of CMOS/TTL data with falling edge or rising edge clock for convenient with a variety of LCD panel controllers. In Single Link, data transmit clock frequency of 112MHz, 48bits of RGB data are transmitted at an effective rate of 784Mbps per LVDS channel. Using a 112MHz clock, the data throughput is 392Mbytes per second. In Dual Link, data transmit clock frequency of 85MHz, 48bits of RGB data are transmitted at an effective rate of 595Mbps per LVDS channel. Using a 85MHz clock, the data throughput is 595Mbytes per second. Features - Wide dot clock range: 25-170MHz suited for...