THC63LVD103 Datasheet | THine Electronics

Description The THC63LVD103 transmitter is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA+ resolutions. The THC63LVD103 converts 35bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream. The transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin. At a transmit clock frequency of 135MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC, VSYNC, DE, CNTL1, CNTL2) are transmitted at an effective rate of 945Mbps per LVDS channel. Features - Wide dot clock range: 8-135MHz suited for NTSC, VGA, SVGA, XGA,SXGA and SXGA+ - - - - - - - - - PLL requires no external ponents Supports spread spectrum clock generator On chip jitter filtering Clock edge selectable Supports reduced swing LVDS for low EMI Power down mode Low power single 3.3V CMOS design 64pin TQFP Backward patible with THC63LVDM63R(18bits) / M83R(24bits) . Block Diagram CMOS/TTL INPUT TA0-6 7 Data Shee LVDS OUTPUT TA +/- TB0-6 7 7 PARALLEL TO SERIAL TB +/- TC0-6 TD0-6 TE0-6 TC +/- TD +/- TE +/- CLK IN (8 to135MHz) RS R/F /PDWN TCLK +/(8 to 135MHz) . Copyright 2001-2006 THine Electronics, Inc. All rights reserved. 1 THine Electronics, Inc. Data Sheet 4 U . .. THC63LVD103 _Rev2.2 Pin Out et4U. TB6 TC0 VCC TC1 TC2 TC3 TC4 GND TC5 TC6 TD0 R/F TD1 TD2 TD3 TD4 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18...