Description
The THC63LVD104S receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions.
Features
- Wide dot clock range: 8-112MHz suited for NTSC,
VGA, SVGA, XGA, and SXGA.
- PLL requires no external components 50% output clock duty cycle TTL clock edge and position programmable(3 step) Power down mode Low power single 2.5V CMOS design TQFP 64pin Pin compatible with THC63LVD104A Fail-safe for Open CLK Input
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DataShee
Block Diagram
LVDS INPUT SERIAL TO.
THC63LVD104S Datasheet
