THC63LVD104A Description
The THC63LVD104A receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to WXGA resolutions.
THC63LVD104A Key Features
- Wide dot clock range: 8-90MHz suited for NTSC
- PLL requires no external ponents
- 50% output clock duty cycle
- TTL clock edge programmable
- Power down mode
- Low power single 3.3V CMOS design
- 64pin TQFP
- Backward patible with THC63LVDF64x