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UG04 - 0.6um ULC

Download the UG04 datasheet PDF. This datasheet also covers the UG09 variant, as both devices belong to the same 0.6um ulc family and are provided as variant models within a single manufacturer datasheet.

Description

The UG series of ULCs is well suited for conversion of medium- to-large sized CPLDs and FPGAs.

Features

  • D High performance ULC family suitable for medium- to large-sized CPLDs and FPGAs D Conversions to over 200,000 FPGA gates D Pin counts to over 300 pins D Any pin-out matched due to limited number of dedicated pads D Advanced 0.6-µm (drawn)/0.45-µm (effective) feature size D Triple-layer or dual-layer metal CMOS technology D High speed performance:.
  • 250-ps typical cell delay.
  • 350-MHz toggle rate D Full range of packages: DIP, SOIC, LCC/PLCC, PQFP/TQFP, PGA/PPGA D 3.3V and/or 5.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (UG09_Temic.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number UG04
Manufacturer Temic
File Size 85.13 KB
Description 0.6um ULC
Datasheet download datasheet UG04 Datasheet

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Other Datasheets by Temic

Part Number Description
UG01 0.6um ULC
UG09 0.6um ULC

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com UG Series 0.6µm ULC Series Description The UG series of ULCs is well suited for conversion of medium- to-large sized CPLDs and FPGAs. Devices are implemented in high-performance CMOS technology with 0.6-µm (drawn) channel lengths, and are capable of supporting flip-flop toggle rates of 350 MHz, operating clock frequencies up to 150 MHz and input to output delays as fast as 5 ns. The architecture of the UG series allows for efficient conversion of many PLD architectures and FPGA device types. A compact RAM cell, along with the large number of available gates allows the implementation of RAM in FPGA architectures that support this feature, as well as JTAG boundary-scan and scan-path testing.
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