CMOS Digital Integrated Circuit Silicon Monolithic
Mobile Peripheral Devices
TC358860XBG converts an Embedded Display Port (eDPTM) video
stream into an MIPI® DSI stream. There are four eDP main link lanes
in TC358860XBG, they can toggle at either 1.62, 2.16, 2.7, 3.24,
4.32, or 5.4 Gbps/link to receive up to 17.28 Gbps (5.4 Gbps * 0.8 *
4) of video stream. The 4-data lanes dual link DSI Tx can transmit up
to 8 Gbps (1 Gbps * 4 * 2) of video stream.
Weight: 40 mg (Typ.)
For input video stream with bandwidth (BW) < 4 Gbps, TC358860XBG can output the video data either
with a single DSI link or performs left-right line split to output the video data stream with dual DSI links.
For input video stream with BW requirements between 4 Gbps and 8 Gbps, left-right line split and dual
DSI links usage is necessary.
TC358860XBG provides a compression engine which compress video data with 2-to-1 ratio. This
enables TC358860XBG to receive 4K @60fps video streams at eDP Rx, compress and send out to a
dual DSI link 4K panel for display. A de-compress engine is expected in the DSI panel.
Host/eDPTx controls/configures TC358860XBG chip by using its AUX channel (I2C over AUX).
TC358860XBG provides mail box register/command queue for host to control/configure/command DSI
panels, too. After host writes to the command queue, TC358860XBG starts DSI “command packets” to
communicate with the DSI panels.
Alternatively, an external I2C master can configure TC358860XBG via I2C bus. Command queue
address can also be access via I2C bus, which means Host can use I2C to access command queue,
which in turn, controls DSI panel parameters.
Please note that host can not use both AUX ch. and I2C bus for register setting simultaneously.
● TC358860XBG follows the following standards:
MIPI Alliance Specification for Display Serial
Interface (DSI) version 1.1, Nov 22 2011
MIPI Alliance Specification for D-PHY Version
1.1, Nov 7 2011
VESA DisplayPort Standard version 1.2a, May
VESA Embedded DisplayPort Standard version
1.4 Feb. 28 2013
● eDP Sink (Receiver)
Bit Rate @ 1.62, 2.16, 2.7, 3.24, 4.32 or
5.4Gbps, Voltage Swing @0.2 to 1.2 V, Pre-
Emphasis Level @3.5dB.
There are four lanes available in eDP main Link,
which can operate in 1-, 2- or 4-lane
Support Single-Stream Transport (SST), not
multi-Stream Transport (MST)
Capable of Full and Fast Link Training
AUX channel with nominal bit rate at 1 Mbps.
Video input data formats supported: RGB666
Absolute maximum pixel rate is 600 Mpixel/s.
Support Alternate Scrambler Seed Reset
(ASSR) is used for content protection, Does not
support HDCP encryption.
- System designer can connect ASSR_Disable
Pad to GND, which prevents eDPTx (Source
device) to disable ASSR mode TC358860XBG.
- In order words, when ASSR_Disable Pad is
grounded, the Source device cannot clear the
bit of the eDP_CONFIGURATION_SET register
(DPCD Address 0010Ah, bit 0) to 0.
No audio SDP, Multi-touch and Backlight DPCD
Support REFCLK from 24 , 25, 26 and 27MHz.
● DSI Transmitter
Dual 4-Data Lane DSI Links with Bi-direction
support at Data Lane 0. Each link can be used in
1-, 2-, 3- or 4-data lane configuration. Maximum
speed at 1.0 Gbps/lane.
Toshiba Electronic Devices & Storage Corporation
1 / 19