TC358870XBG Datasheet | Toshiba

Overview TC358870XBG, Ultra HD to DSI, bridge converts high resolution (higher than 4 Gbps) HDMI® stream to MIPI® DSI Tx video. It is a follow up device of TC358779XBG, without scalar functionality. The HDMI-RX runs at 297 MHz to carry up to 7.2 Gbps video stream. It requires dual link MIPI DSI Tx, 1 Gbps/data lane, to transmit out a maximum 7.2 Gbps video data. P-VFBGA80-0707-0.65-001 Weight: 67 mg (Typ.) The bridge chip is necessary for current and next generation Application Processors to drive a (dual) DSI link display by using its HDMI Tx output port. Features - HDMI-RX Interface - HDMI 1.4b - Video Formats Support (Up to 4K×2K / 30fps), maximum 24 bps (bit-per-pixel) no deep color support - RGB, YCb Cr444: 24-bpp - YCb Cr422: 24-bpp - Color Conversion - 4:2:2 to 4:4:4 is supported - 4:4:4: to 4:2:2 is supported - RGB888 to YCb Cr (4:4:4 / 4:2:2) is supported - YCb Cr (4:4:4 / 4:2:2) to RGB888/666 is supported - Note: for RGB666 (R=R[5:0],2'b00, G=G[5:0],2'b00, B=G[5:0],2'b00) - Maximum HDMI clock speed: 297 MHz - Audio Supports - Internal Audio PLL to track N/CTS value transmitted by the ACR packet. - 3D Support - Support HDCP1.4 decryptions (optional) - EDID Support, Release A, Revision 1 (Feb 9, 2000) - First 128 byte (EDID 1.3 structure) - First E-EDID Extension: 128 bytes of CEA Extension version 3 (specified in CEA-861-D) - Embedded 1K-byte SRAM (EDID_SRAM) - Does not support Audio Return Path and HDMI Ethernet Channels - DSI TX Interface - MIPI DSI pliant (Version 1.1 22 November 2011) - Dual links DSI (DSI0 and DSI1), each link supports 4 data lanes @1 Gbps/ data lane - DSI0 carries the left half data of HDMI Rx video stream and DSI1 carries the right one at the default configuration. - Left or right data can be assigned/programmed to either DSI Tx link - The maximum length of each half is limited to 2048-pixel plus up to full length overlap, DSI0 data length could be different from that of DSI1's - The maximum Hsync skew between DSI0 and DSI1 can be...