TC55V8512FT Datasheet | Toshiba

DESCRIPTION The TC55V8512J/FT is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 524,288 words by 8 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it operates from a single 3.3 V power supply. Chip enable ( CE ) can be used to place the device in a low-power mode, and output enable ( OE ) provides fast memory access. This device is well suited to cache memory applications where high-speed access and high-speed storage are required. All inputs and outputs are directly LVTTL patible. The TC55V8512J/FT is available in plastic 36-pin SOJ and 44-pin TSOP with 400mil width for high density surface assembly. FEATURES - Fast access time (the following are maximum values) TC55V8512J/FT-12:12 ns TC55V8512J/FT-15:15 ns Low-power dissipation (the following are maximum values) Cycle Time Operation (max) 12 170 15 140 20 130 25 110 ns m A - - - - - - Single power supply voltage of 3.3 V ± 0.3 V Fully static operation All inputs and outputs are LVTTL patible Output buffer control using OE Package: SOJ36-P-400-1.27 (J) (Weight: 1.35 g typ) TSOP II44-P-400-0.80 (FT) (Weight: 0.45 g typ) Standby:4 m A (both devices) PIN ASSIGNMENT (TOP VIEW) 36 PIN SOJ 44 PIN TSOP PIN NAMES A0 to A18 NC NC A17 A3 A2 A1 A0 CE I/O1 I/O2 VDD GND I/O3 I/O4 WE A16 A15 A14 A13 A18 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A4 A5 A6 A7 OE I/O8 I/O7 GND VDD I/O6 I/O5 A8 A9 A10 A11 A12 NU NC NC I/O1 to I/O8 Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Power (+3.3 V) Ground No Connection Not Usable (Input) A17 A3 A2 A1 A0 CE I/O1 I/O2 VDD GND I/O3 I/O4 WE A16 A15 A14 A13 A18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A4 A5 A6 A7 OE I/O8 I/O7 GND VDD I/O6 I/O5 A8 A9 A10 A11 A12 NU VDD GND NC NU (TC55V8512J) (TC55V8512...