Datasheet4U Logo Datasheet4U.com

TC74AC74FT - Dual D-Type Flip-Flop

General Description

2.

The TC74AC74FT is an advanced high speed CMOS D-FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology.

Key Features

  • (1) Wide operating temperature range: Topr = -40 to 125  (Note 1) (2) High speed: fMAX = 200 MHz (typ. ) at VCC = 5.0 V (3) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25 (4) High noise immunity: VNIH = VNIL = 28% VCC (min) (5) Output current: |IOH|/IOL = 24 mA (min) (VCC = 4.5 V) (6) Balanced propagation delays: tPLH ≈ tPHL (7) Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V (8) Pin and function compatible with 74F74. Note 1: Operating Range spec of Topr = -40  to 125  is appli.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
TC74AC74FN DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR Toshiba Semiconductor
TC74AC00FN QUAD 2 - INPUT NAND GATE Toshiba Semiconductor
TC74AC02F Quad 2-Input NOR Gate Toshiba Semiconductor
TC74AC02P Quad 2-Input NOR Gate Toshiba Semiconductor
TC74AC04F HEX INVERTER Toshiba Semiconductor

Other Datasheets by Toshiba

Part Number Description
TC74AC74F Dual D-Type Flip-Flop
TC74AC74P Dual D-Type Flip-Flop
TC74AC00F Quad 2-Input NAND Gate
TC74AC00FT Quad 2-Input NAND Gate
TC74AC00P Quad 2-Input NAND Gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CMOS Digital Integrated Circuits Silicon Monolithic TC74AC74FT TC74AC74FT 1. Functional Description • Dual D-Type Flip-Flop with Preset and Clear 2. General The TC74AC74FT is an advanced high speed CMOS D-FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input to an "L" level. All inputs are equipped with protection circuits against static discharge or transient excess voltage. 3.