Datasheet4U Logo Datasheet4U.com

TC74HC138AFN - 3-TO-8 Line Decoder

This page provides the datasheet information for the TC74HC138AFN, a member of the TC74HC138 3-TO-8 Line Decoder family.

Features

  • High speed: tpd = 16 ns (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Output drive capability:.

📥 Download Datasheet

Datasheet preview – TC74HC138AFN

📁 Similar Datasheet

  • TC74HC112AF - Dual J-K Flip Flop (Toshiba Semiconductor)
  • TC74HC112AFN - Dual J-K Flip-Flop (Toshiba Semiconductor)
  • TC74HC112AP - Dual J-K Flip-Flop (Toshiba Semiconductor)
  • TC74HC155P - TTL DUAL 2-TO-4-LINE DECODER / 3-TO-8-LINE DECODER (ETC)
  • TC74HC00AF - Quad 2-Input NAND Gate (Toshiba Semiconductor)
  • TC74HC00AP - Quad 2-Input NAND Gate (Toshiba Semiconductor)
  • TC74HC02AF - Quad 2-Input NOR Gate (Toshiba Semiconductor)
  • TC74HC02AFN - Quad 2-Input NOR Gate (Toshiba Semiconductor)
  • TC74HC02AP - Quad 2-Input NOR Gate (Toshiba Semiconductor)
  • TC74HC03AF - Quad 2-Input NAND Gate (Toshiba Semiconductor)
Other Datasheets by Toshiba

Full PDF Text Transcription

Click to expand full text
TC74HC138AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC138AP, TC74HC138AF 3-to-8 Line Decoder The TC74HC138A is a high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs ( Y0 - Y7 ) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high. G1, G2A , and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems.
Published: |