Datasheet4U Logo Datasheet4U.com

TC74HC139AP - DUAL 2 TO 4 LINE DECODER

Download the TC74HC139AP datasheet PDF (TC74HC139 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for dual 2 to 4 line decoder.

Features

  • High speed: tpd = 16 ns (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Output drive capability: 10 LSTTL loads.
  • Symmetrical output impedance: |IOH| = IOL = 4 mA (min).
  • Balanced propagation dela.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74HC139_Toshiba.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

  • TC74HC112AF - Dual J-K Flip Flop (Toshiba Semiconductor)
  • TC74HC112AFN - Dual J-K Flip-Flop (Toshiba Semiconductor)
  • TC74HC112AP - Dual J-K Flip-Flop (Toshiba Semiconductor)
  • TC74HC155P - TTL DUAL 2-TO-4-LINE DECODER / 3-TO-8-LINE DECODER (ETC)
  • TC74HC00AF - Quad 2-Input NAND Gate (Toshiba Semiconductor)
  • TC74HC00AP - Quad 2-Input NAND Gate (Toshiba Semiconductor)
  • TC74HC02AF - Quad 2-Input NOR Gate (Toshiba Semiconductor)
  • TC74HC02AFN - Quad 2-Input NOR Gate (Toshiba Semiconductor)
  • TC74HC02AP - Quad 2-Input NOR Gate (Toshiba Semiconductor)
  • TC74HC03AF - Quad 2-Input NAND Gate (Toshiba Semiconductor)
Other Datasheets by Toshiba

Full PDF Text Transcription

Click to expand full text
TC74HC139AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC139AP, TC74HC139AF Dual 2-to-4 Line Decoder The TC74HC139A is a high speed CMOS 2-to-4 LINE DECODER/DEMULTIPLEXER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The active low enable input can be used for gating or it can be used as a data input for demultiplexing applications. When the enable input is held “H”, all four outputs are fixed at a high logic level independent of the other inputs. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: tpd = 16 ns (typ.
Published: |