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TC74HC155AF - Dual 2-to-4 Line Decoder 3-to-8 Line Decoder

Download the TC74HC155AF datasheet PDF. This datasheet also covers the TC74HC155AP variant, as both devices belong to the same dual 2-to-4 line decoder 3-to-8 line decoder family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • dual 1-to-4 line demultiplexers with individual strobe input (1G and 2G), individual data inputs (1C and 2C) and common binary address inputs (A and B). When both decoders are enabled by the strobes, the inverted output of 1C data and non-inverted output of 2C data will be brought to the selected output pins of each section. A 1-to-8 line demultiplexer can be easily built up by providing a data signal to both the 1C and 2C inputs; the output order will be 1Y3 (MSB), 1Y2, 1Y1, 1Y0, 2Y3, 2Y2, 2Y1,.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74HC155AP-Toshiba.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number TC74HC155AF
Manufacturer Toshiba
File Size 233.37 KB
Description Dual 2-to-4 Line Decoder 3-to-8 Line Decoder
Datasheet download datasheet TC74HC155AF Datasheet

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Other Datasheets by Toshiba

Part Number Description
TC74HC155AP Dual 2-to-4 Line Decoder 3-to-8 Line Decoder
TC74HC151AF 8-CHANNEL MULTIPLEXER
TC74HC151AFN 8-CHANNEL MULTIPLEXER
TC74HC151AP 8-CHANNEL MULTIPLEXER
TC74HC153AF Dual 4-Channel Multiplexer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74HC155AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC155AP, TC74HC155AF Dual 2-to-4 Line Decoder 3-to-8 Line Decoder The TC74HC155A is a high speed CMOS DUAL 2-to-4 LINE DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. It features dual 1-to-4 line demultiplexers with individual strobe input (1G and 2G), individual data inputs (1C and 2C) and common binary address inputs (A and B). When both decoders are enabled by the strobes, the inverted output of 1C data and non-inverted output of 2C data will be brought to the selected output pins of each section.