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TC74HC4024AP - 7-Stage Binary Counter

Key Features

  • High speed: fmax = 70 MHz (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Output drive capability: 10 LSTTL loads.
  • Symmetrical output impedance: |IOH| = IOL = 4 mA (min).
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Wide operating voltage range: VCC (opr) = 2 to 6 V.
  • Pin and function compatible with 4024B Pin Assignment TC74HC4024AP TC74HC4.

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Full PDF Text Transcription (Reference)

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TC74HC4024AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC4024AP, TC74HC4024AF 7-Stage Binary Counter The TC74HC4024A is a high speed CMOS 7-STAGE BINARY COUNTER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. A negative transition on the CK input brings one increment to the counter. A CLR input is used to reset the counter to the all low level state. A high level at CLR accomplishes the reset function. All divided output stages are provided, and the last stage, 1/128 divided frequency will be obtained. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: fmax = 70 MHz (typ.