TC74HC4024AF Overview
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. A negative transition on the CK input brings one increment to the counter. A CLR input is used to reset the counter to the all low level state.
TC74HC4024AF Key Features
- High speed: fmax = 70 MHz (typ.) at VCC = 5 V
- Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
- High noise immunity: VNIH = VNIL = 28% VCC (min)
- Output drive capability: 10 LSTTL loads
- Symmetrical output impedance: |IOH| = IOL = 4 mA (min)
- Balanced propagation delays: tpLH ∼- tpHL
- Wide operating voltage range: VCC (opr) = 2 to 6 V
- Pin and function patible with 4024B